ArticleSensors (Basel, Switzerland)2019
A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements.
Article in Sensors (Basel, Switzerland), 2019. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 4 papers.
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Who cites it
4 citing papers in PubMed.
- A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters.Sensors (Basel, Switzerland) · 2023Article
- Systematization and Comparison of the Binary Successive Approximation Variants.Sensors (Basel, Switzerland) · 2021Article
- A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor.Sensors (Basel, Switzerland) · 2021Article
- An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction.Sensors (Basel, Switzerland) · 2020Article
Corrections and comments
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Authors and funding
3 authors.
Funding
Abstract
The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs-Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control.
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Registered trials
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