ArticleFrontiers in neuroscience2018
Breaking Liebig's Law: An Advanced Multipurpose Neuromorphic Engine.
Article in Frontiers in neuroscience, 2018. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 3 papers.
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Who cites it
3 citing papers in PubMed.
- Memory-efficient neurons and synapses for spike-timing-dependent-plasticity in large-scale spiking networks.Frontiers in neuroscience · 2024Article
- Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain.Frontiers in neuroscience · 2018Review
- GPUs Outperform Current HPC and Neuromorphic Solutions in Terms of Speed and Energy When Simulating a Highly-Connected Cortical Model.Frontiers in neuroscience · 2018Article
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Authors and funding
2 authors.
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Abstract
We present a massively-parallel scalable multi-purpose neuromorphic engine. All existing neuromorphic hardware systems suffer from Liebig's law (that the performance of the system is limited by the component in shortest supply) as they have fixed numbers of dedicated neurons and synapses for specific types of plasticity. For any application, it is always the availability of one of these components that limits the size of the model, leaving the others unused. To overcome this problem, our engine adopts a unique novel architecture: an array of identical components, each of which can be configured as a leaky-integrate-and-fire (LIF) neuron, a learning-synapse, or an axon with trainable delay. Spike timing dependent plasticity (STDP) and spike timing dependent delay plasticity (STDDP) are the two supported learning rules. All the parameters are stored in the SRAMs such that runtime reconfiguration is supported. As a proof of concept, we have implemented a prototype system with 16 neural engines, each of which consists of 32768 (32k) components, yielding half a million components, on an entry level FPGA (Altera Cyclone V). We verified the prototype system with measurement results. To demonstrate that our neuromorphic engine is a high performance and scalable digital design, we implemented it using TSMC 28nm HPC technology. Place and route results using Cadence Innovus with a clock frequency of 2.5 GHz show that this engine achieves an excellent area efficiency of 1.68 μm
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